This invention relates to cathode ray tube controllers and, more specifically, to a circuit for generating video control signals, as well as character address signals, for providing a cathode ray tube character display.
Cathode ray tube controllers for the digital control of video displays are common in the prior art. In particular, systems for generating alpha-numeric character displays are commonly provided in word processing, accounting, communication, and general computer peripheral applications.
Because of the need, in generating a cathode ray tube video display, to continually and repetitively refresh the information written on the display, it is common to utilize a writable memory (RAM) having a discrete addressable location for each character to be displayed on the video screen. Complex systems are provided for sequentially addressing this RAM to provide, at the output of the RAM, a sequence of digital words identifying the characters to be visually displayed at successive character locations on the screen.
These digital words typically supply the input to a character generator read only memory (ROM). This character generator ROM is additionally supplied with data words which identify the particular raster lines within the letter which, at any time, are being scanned by the cathode ray gun. In response to these inputs, the character generator ROM provides an output word identifying the graphical content of each cathode ray tube raster line required to generate the identified characters. A shift register, coupled to the output of a character generator ROM, generates pulse signals, in sequence, for controlling the on and off state of the cathode ray gun to graphically reproduce the characters.
The present invention deals specifically with the electronic system used for generating the input address data words to the refresh RAM and for providing other video control signals, such as blanking signals and sync signals.
In the prior art, these address and video control signals have typically been provided by a pair of horizontal counters and a pair of vertical counters. The first counter in the horizontal pair has been used to provide video control signals, such as horizontal sync signals and blanking signals. This first counter counts a system clock, to whatever counting base is needed, based on the clock rate, to produce a horizontal sync signal when the counter is full. The counter thus repetitively counts until full, generates a horizontal sync signal, and then repeats the count.
The second horizontal counter is slaved to the first, so that, when the first counter generates a count indicating that the blanked margin on the left-hand side of the screen has been traced, the second counter beings its count. This second counter typically includes one count for each character space in the portion of the screen actually to be filled with character information. The second counter thus finishes its count at the location of the right-hand margin on the screen, and the first horizontal counter continues its count until retrace occurs at the horizontal sync point.
The vertical counter pair operates in a similar manner, with the first vertical counter providing video control signals, such as the vertical sync signal, and the second counter, slaved to the first, counting actual character line locations in the non-blanked vertical portion of the cathode ray tube screen. The first vertical counter is slaved to the sync output of the first horizontal counter, since the first horizontal counter provides one sync output for each raster line. The first vertical counter thus counts raster lines throughout the entire vertical dimension of the cathode ray tube screen.
The second horizontal counter and second vertical counter provide x and y data matrix address information to define cells for the characters to be displayed on the screen. In order to linearize this data, for storage in a one-dimensional refresh RAM, the prior art has commonly utilized a ROM as a translator for the output of the second vertical counter. If the second horizontal counter counted an even binary multiple of horizontal character widths, across the non-blanked portion of the cathode ray tube screen, this ROM would not be necessary, since the horizontal and vertical address outputs could be concatenated to provide a discrete address for the refresh RAM without leaving gaps within the refresh ROM between horizontal lines.
Since an 80-character width line is common, however, and since the numeral 80 is not an integral binary multiple, the translating ROM provides base addresses, with each successive base address offset from the previous base address, in binary form, by 80. This permits the output of the translating ROM and the second horizontal counter to be added, the sum providing the address for the refresh RAM.
The counter chains required by the prior art systems described above, and particularly the first horizontal counter and the first vertical counter, incorporate a large amount of digital logic circuitry which makes the systems relatively expensive and decreases their reliability.
Furthermore, these prior art systems present extreme problems when partial screen scrolling is to be accomplished. From the above description, it will be understood that, by simply loading an offset into the second vertical counter, and by periodically increasing that offset, the entire screen display can be vertically scrolled. Such scrolling is desirable, for example, when the screen is filled and additional lines are added by an operator.
It has been found advantageous in the prior art to scroll most of the character lines on the screen while holding some character lines stationary, such as, for example, a base line providing margin information, etc. The prior art systems were able to provide such partial scrolling with stationary screen portions, during scrolling, only through the use of expensive and complex digital logic networks, further substantially adding to the cost of prior art systems.